Stratix 10 GX: H-Tile Transceiver - *Direct* dynamic reconfiguration

Hi dlim,

Thanks for your answer and suggestions.

1. No, I don't perform re-calibration. The documentation says that re-calibration is necessary when the data rate or protocol mode is changed. So I thought that this isn't necessary when "only" the analog PMA settings are changed. Anyway, I will try to add this to my control sequence.

2. We changed through pretty much the complete valid value range in the lab. Of course, especially we tried a few changes from min to max values. But there is absolutely no visible difference, so I really guess that the change is not "propagated" to the actual high-speed driver stage although the changed values can be read back from the reconfiguration interface.

3. Also here, we tried changing from min to max VOD setting only. And there is no visible difference in the eye of the output signal.

4. Yes, we use an oscilloscope. The setup is definitely fine. We have used the "Board Test System" software initially with the "qts_fmca" design to verify that the programming and control of the FPGA from the PC side works as expected. Here we can see changes on pre-emphasis and VOD propagating directly to the signal eye.

Additional note:
My answers to points 2-4 aren't 100% true. We actually have the "Stratix 10 GX FPGA Development Kit" board and use the following signal chain:

Stratix 10 Transceiver PHY TX -> FMC-A -> Electrical-2-Optical Board from another supplier -> Optical cable -> Optical-2-Electrical Board from the other supplier -> SMA connector -> Oscilloscope

With the oscilloscope we look at the actual waveform of the received signal AND we measure the eye diagram.

So we can't see the Transceiver PHY TX output directly at all. At the moment we don't have an FMC->SMA adapter board, so there is no possibility to probe the TX output signals directly.

BUT: as I wrote, we have used the related "Board Test System" example design as a first shot and could see direct influence of the analog TX settings to the eye measurement results. As of now we can't see any (even slight) influence of any setting changes that I do via my self-coded reconfiguration controller.

Again, I appreciate any comments/helpful tipps very much.

Best regards.
Sebastian

Hi dlim,

thanks for your answer and suggestions. Transceiver Toolkit is unfortunately not an option for the moment. We only have one license available and the lab PC is not very capable. So for synthesizing/generating the .sof files I use a powerful Linux workstation which can't be directly connected to the Hardware.

I have found a workaround for the moment: I found the tcl script template

Ttk_helper_s10.tcl

on the following site:
https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Stratix-10-GX-Series/ta-p/735749

This works in combination with a slightly modified qts_fmca.sof design from the Board Test System examples. I finally managed to control data types and analog settings for each channel individually from the tcl System Console and I can now put together some scripts for the lab engineer to easily modify the individual settings with single tcl commands.

This is OK for the moment, the initial signal quality evaluation.

But as the qts_fmca design isn't exactly what we need for the final FPGA implementation, I am still struggling to implement a self-coded design making use of the dynamic reconfiguration flow. I had a look at the Transceiver Toolkit for Intel Stratix 10 devices presentation from the Intel Training Catalogue. It states that by just enabling the dynamic reconfiguration and the "ADME" features in the Native PHY parameter editor, the access from Quartus Prime should be made available. My understanding is from that training that no Platform Designer action is necessary for that and that the System Console access should also be possible (because, as stated above, we can't use the Transceiver Toolkit at the moment).

In my initial trial this doesn't work, I load the tcl procedures into the System Console, but other than for the qts_fmca design, the initial check of the tcl script states that it couldn't find any PHY instances on the design.

I tried to do a top level RTL code which instantiates the PHY instance (one PHY with 2 channels), the related ATX PLL and reset controller instances and some simple top level low speed logic. But when the ADME is used, I have not yet understood how to connect the reconfig_* inputs/outputs to the PHY instance. There are no top level signals that drive this interface. Do I leave them open/unconnected? Or do I have to connect at least clock and reset?

If you prefer that I open another/separate request to this topic as we are iterating over several approaches in this thread, please let me know.

Again, thanks in advance for any hints or suggestions.

Best regards,
Sebastian

Hi dlim,

thanks a lot for your answers. I will check all the suggestions and see how far I will get.

Regarding item 1: the downloaded file "S10_GX_devkit_ttk.qar" is only 590kB in size and when I try to open it in Quartus (I am using version 18.1.0.222) it gives me an error message:

"Failed to restore S10_GX_devkit.TTK.qar
Evaluation of Tcl script /teetools/misc/intel/qpp/18.1.0.222/quartus/common/tcl/apps/qpm/qar.tcl unsuccessful"

Maybe I am trying to open it in the wrong way. Can you check the file again?

Thanks a lot in advance. Best regards,
Sebastian

Hi dlim,

Sorry for not replying for some time. It's a little bit complicated. I didn't have time to follow up on this for last 1,5 weeks. And won't be able to do so for another week or so.

I will try again after that and let you know if there is progress. If you need to close this thread, let me know, I think some of your hints/links will be helpful to solve this in the end.

Best regards,
Sebastian