Stratix 10 GX: H-Tile Transceiver - *Direct* dynamic reconfiguration

Hi dlim,

thanks for your answer and suggestions. Transceiver Toolkit is unfortunately not an option for the moment. We only have one license available and the lab PC is not very capable. So for synthesizing/generating the .sof files I use a powerful Linux workstation which can't be directly connected to the Hardware.

I have found a workaround for the moment: I found the tcl script template

Ttk_helper_s10.tcl

on the following site:
https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Stratix-10-GX-Series/ta-p/735749

This works in combination with a slightly modified qts_fmca.sof design from the Board Test System examples. I finally managed to control data types and analog settings for each channel individually from the tcl System Console and I can now put together some scripts for the lab engineer to easily modify the individual settings with single tcl commands.

This is OK for the moment, the initial signal quality evaluation.

But as the qts_fmca design isn't exactly what we need for the final FPGA implementation, I am still struggling to implement a self-coded design making use of the dynamic reconfiguration flow. I had a look at the Transceiver Toolkit for Intel Stratix 10 devices presentation from the Intel Training Catalogue. It states that by just enabling the dynamic reconfiguration and the "ADME" features in the Native PHY parameter editor, the access from Quartus Prime should be made available. My understanding is from that training that no Platform Designer action is necessary for that and that the System Console access should also be possible (because, as stated above, we can't use the Transceiver Toolkit at the moment).

In my initial trial this doesn't work, I load the tcl procedures into the System Console, but other than for the qts_fmca design, the initial check of the tcl script states that it couldn't find any PHY instances on the design.

I tried to do a top level RTL code which instantiates the PHY instance (one PHY with 2 channels), the related ATX PLL and reset controller instances and some simple top level low speed logic. But when the ADME is used, I have not yet understood how to connect the reconfig_* inputs/outputs to the PHY instance. There are no top level signals that drive this interface. Do I leave them open/unconnected? Or do I have to connect at least clock and reset?

If you prefer that I open another/separate request to this topic as we are iterating over several approaches in this thread, please let me know.

Again, thanks in advance for any hints or suggestions.

Best regards,
Sebastian