Stratix 10 CKEXT Drive Level 32 GHz Clock

The +1.9 dBm lower CKEXT requirement should be viewed as a performance‑validated limit rather than a hard functional cutoff: if the CKEXT drive drops below +1.9 dBm, the Stratix 10 will generally continue to operate, but you may encounter reduced jitter margin, higher BER, or less‑stable PLL locking, and while a drive level around 0 dBm usually won’t prevent the clock path or PLL from functioning outright, it does fall outside Intel’s guaranteed operating conditions, meaning that signal integrity degrades and published timing and jitter specifications may no longer be met—so it’s best to treat +1.9 dBm as the minimum level needed for full, spec‑compliant transceiver and PLL performance.