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tm1701's avatar
tm1701
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3 years ago
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Stratix 10 - pin BB17 PCIE_RT_S10_PERSTn

Hello,

I have a question regarding PIN BB17 of the Stratix 10 MX FPGA.

According to the Stratix-10 schematic BB17 is an output pin of IO Bank 3A that's connected to a Max10 (see page 32 and page 45 of the schematic). The name of the Signal is PCIE_RT_S10_PERSTn.

The Pin is not mentioned in the Stratix 10 User-Guide.

What's the purpose of the Pin, and how do we need to use it in a Design using a PCI Express Hard IP-Core configured as Root-Port?

Perstn is a PCIe reset and RT in the signal name indicates it's a signal for the Root-Port IP-Core..

Thanks in advance for any help.

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  • hareesh's avatar
    hareesh
    3 years ago

    Hi,


    this pin is used to drive the PERST to the endpoint that is connected to the J7 connector. 3B GPIO output goes to Max10, and then the Max10 will assert the PERST to EP (PCIE_RT_PERST). This should be driven by user logic in the FPGA design and can be based on the PERST output of the RP IP itself if the PERST input to it is coming from elsewhere (double check where the PERST input is coming from.. in some devkit, the GPIO output loops back and drives the RP PERST as well as the EP, so in that case PERST can be driven by some independent logic).


10 Replies

  • hareesh's avatar
    hareesh
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,


    this pin is used to drive the PERST to the endpoint that is connected to the J7 connector. 3B GPIO output goes to Max10, and then the Max10 will assert the PERST to EP (PCIE_RT_PERST). This should be driven by user logic in the FPGA design and can be based on the PERST output of the RP IP itself if the PERST input to it is coming from elsewhere (double check where the PERST input is coming from.. in some devkit, the GPIO output loops back and drives the RP PERST as well as the EP, so in that case PERST can be driven by some independent logic).


  • hareesh's avatar
    hareesh
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,

    Thanks for contacting Intel. I'm assigned to support request.

    I'll investigate and get back to you soon. Thanks for your patience.

    Best regards,

    Hareesh B.


  • hareesh's avatar
    hareesh
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    3 years ago

    Hi,


    I am discussing this with the team. we need some more time.


  • tm1701's avatar
    tm1701
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    3 years ago

    Hi,

    thank your for the response.

    According to the PCIe Specification the PERST Pin (on connector J7) indicates when the applied main power is within the specified tolerance and stable.
    Just for my understanding, if I were to drive pin BB17 PCIE_RT_S10_PERSTn constant High, would the Max10 then only assert the PERST to EP Pin if the above condition is fulfilled, i.e. main power is stable?

    @hareesh wrote:
    [...] and can be based on the PERST output of the RP IP itself[...]

    Regarding the above statement, could you please explain which PERST output of the RP IP you mean?
    I am only aware of a Perst input to the RP IP-Core itself, which isn't driven by user logic but connects to PIN B10 S10_PCIE_PERSTn1.

    Kind regards!

  • hareesh's avatar
    hareesh
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    3 years ago

    Hi,

    do you have any queries?


    still, do you need help?


    • tm1701's avatar
      tm1701
      Icon for New Contributor rankNew Contributor
      3 years ago

      I've posted a question before regarding how the input of the pin should be derived from a output of the RP IP itself.

      Else I do not have any further queries.

  • hareesh's avatar
    hareesh
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,

    I am discussing this with the team. please give me some time.

  • hareesh's avatar
    hareesh
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi,

    3B GPIO output goes to Max10, and then the Max10 will assert the PERST to EP (PCIE_RT_PERST). This should be driven by user logic in the FPGA design



  • hareesh's avatar
    hareesh
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.