hareesh
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Re: Cyclone 10GX Reference Design - Cyclone10GX_PCIeGen2x4_DMA_18_0 fails during enumeration.
As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.Re: Cyclone 10GX Reference Design - Cyclone10GX_PCIeGen2x4_DMA_18_0 fails during enumeration.
Hi, You are using the new version of Quartus. the problem is that the example design can support the Quartus 18.0 version. In the newer version, you can see some more new features to that IP like new signals, data width, etc.. if you update the older designs ip's in a new version the signals of the new version ip's will be in an open state only. because of that, it shows errors. if you need to compile this please use Quarts 18.0 version only. in the above image, you can see successfully compiled in Quartus 18.0.
