tm1701
New Contributor
New ContributorStratix 10 - pin BB17 PCIE_RT_S10_PERSTn
Hello, I have a question regarding PIN BB17 of the Stratix 10 MX FPGA. According to the Stratix-10 schematic BB17 is an output pin of IO Bank 3A that's connected to a Max10 (see page 32 and page 4...
Hi,
this pin is used to drive the PERST to the endpoint that is connected to the J7 connector. 3B GPIO output goes to Max10, and then the Max10 will assert the PERST to EP (PCIE_RT_PERST). This should be driven by user logic in the FPGA design and can be based on the PERST output of the RP IP itself if the PERST input to it is coming from elsewhere (double check where the PERST input is coming from.. in some devkit, the GPIO output loops back and drives the RP PERST as well as the EP, so in that case PERST can be driven by some independent logic).
