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Honored ContributorStrange PLL Clock causing me failing paths in cyc V design
Dear all,
TimeQuest is warning me of a failing path in my Altera Cyclone V FPGA design. It says failing path with:Slack______From Node ____________________________________ ____to Node __________Launch Clock ____________________________________________________________________________Latch clock____Relationship __Clock Skew ___Data Delay
-9.115 ____ io_control:io_control_inst1|data_out _______ dq _______ pll_inst_100|pll_100_inst|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk ______ clk_100____ 10.000 ____ -10.144______2.901
flopping_data_out_proc : process(CLK, RESET)begin
if (RESET = '0') then
data_out <= (others => '0');
elsif (rising_edge(CLK)) then
data_out <= Fin_DATA_ram; -- comes from inside FPGA Design
end if;
end process flopping_data_out_proc;
mux_data_out_proc : process(slrd_en, data_out)
begin
if (slrd_en = '0') then
DATA <= data_out; -- DATA is output of IO Control and wired to DQ
else
DATA <= (others => 'Z');
end if;
end process;Warning (332049): Ignored create_clock at SDC1.sdc(2): Incorrect assignment for clock. Source node: CLOCK_50_B5B already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated.
Info (332050): create_clock -name CLK1 -period 20.0 13 Replies
Altera_ForumSomewhere, you have another constraint targeting the port CLOCK_50_B5B based on the warning you got. Whatever that constraint is is part of what's messing things up.
The failing path report is indicating that clk_100, your virtual clock, is the latch clock for the failing path, implying that the failing path is an output path. Is this correct? Is clk_100 driving whatever device you are feeding? Check your set_input_delay and set_output_delay constraints. Make sure that the correct virtual clock is referenced in them (upstream device virtual clock for set_input_delay; downstream virtual device clock for set_output_delay). Maybe just post your whole .sdc! That might make it easier to figure this out.- Altera_Forum--- Quote Start --- You're using the same input port for 2 different clock domains. As the warning says, you should include -add to have both clocks input on the same port. Do you have something on your board that switches between generating 50 MHz and 100 MHz to this same port? divclk looks like the output of your PLL. --- Quote End --- Hello, where do you see this? In the SDC file I have:
Clock_50_B5B is reference clock for the LPDDR2 Hardmemory Controller PLL (165.02 MHz + 330MHz). CLOCK_50_B6A is driving the 50 MHz instances on FPGA and is also the reference clock for the 100 MHz PLL. Is this causing me the failing path warning in time quest? How do I have to interpret the failing path? Is not the above mentioned failing path telling me that I have a skew of 10 ns which is caused with the last flopping of output data in IO_Control? There is no switching between 50 and 100 MHz.create_clock -name CLK1 -period 20.0 create_clock -name CLK2 -period 20.0 create_clock -period 10 -name clk_100 - Altera_Forum
You're using the same input port for 2 different clock domains. As the warning says, you should include -add to have both clocks input on the same port. Do you have something on your board that switches between generating 50 MHz and 100 MHz to this same port?
divclk looks like the output of your PLL.
