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Altera_Forum
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7 years ago

Strange PLL Clock causing me failing paths in cyc V design

Dear all, TimeQuest is warning me of a failing path in my Altera Cyclone V FPGA design. It says failing path with: Slack______From Node ____________________________________ ____to No...
Altera_Forum's avatar
Altera_Forum
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7 years ago

You're using the same input port for 2 different clock domains. As the warning says, you should include -add to have both clocks input on the same port. Do you have something on your board that switches between generating 50 MHz and 100 MHz to this same port?

divclk looks like the output of your PLL.