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You're using the same input port for 2 different clock domains. As the warning says, you should include -add to have both clocks input on the same port. Do you have something on your board that switches between generating 50 MHz and 100 MHz to this same port?
divclk looks like the output of your PLL.
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Hello,
where do you see this? In the SDC file I have:
create_clock -name CLK1 -period 20.0
create_clock -name CLK2 -period 20.0
create_clock -period 10 -name clk_100
Clock_50_B5B is reference clock for the LPDDR2 Hardmemory Controller PLL (165.02 MHz + 330MHz). CLOCK_50_B6A is driving the 50 MHz instances on FPGA and is also the reference clock for the 100 MHz PLL.
Is this causing me the failing path warning in time quest? How do I have to interpret the failing path? Is not the above mentioned failing path telling me that I have a skew of 10 ns which is caused with the last flopping of output data in IO_Control?
There is no switching between 50 and 100 MHz.
Honored Contributor
