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Honored Contributor
Honored ContributorStrange PLL Clock causing me failing paths in cyc V design
Dear all, TimeQuest is warning me of a failing path in my Altera Cyclone V FPGA design. It says failing path with: Slack______From Node ____________________________________ ____to No...
Altera_ForumHonored Contributor
Honored ContributorSomewhere, you have another constraint targeting the port CLOCK_50_B5B based on the warning you got. Whatever that constraint is is part of what's messing things up.
The failing path report is indicating that clk_100, your virtual clock, is the latch clock for the failing path, implying that the failing path is an output path. Is this correct? Is clk_100 driving whatever device you are feeding? Check your set_input_delay and set_output_delay constraints. Make sure that the correct virtual clock is referenced in them (upstream device virtual clock for set_input_delay; downstream virtual device clock for set_output_delay). Maybe just post your whole .sdc! That might make it easier to figure this out.
