Honored ContributorJust want to ask a very simple question but it troubled me alot,
let say i have to input a and b with the format of std_logic_vector(7 downto 0) and output c with the format of std_logic_vector(15 downto 0) and let say i have c < = a + b how do i resize the input so that the result is will be compatible with the output c ??
Honored ContributorTry this method(one of many) if your values are meant to be signed, otherwise use unsigned
c <= std_logic_vector(resize(signed(a),16) + resize(signed(b),16));Honored Contributorthanks alot..it works!!!! may i know what those alternative methods?
Honored ContributorOne more way is to do the extension manually i.e. declare two intermediate signals of 16 bits each (a_16,b_16) each assigned the sign extended a,b version by inseting zeros(for positive values) or ones(for negative values) then add up a_16 and b_16 to c.
another way is to do addition as 8 bits with carry then sign extend the result onto c another way is to instantiate an altera adder and enter the various widths. note for adding two 8 bit values you only need 9 bits result and not 16 bits.Honored Contributorthanks alot kaz!!!
