std_logic_vector

One more way is to do the extension manually i.e. declare two intermediate signals of 16 bits each (a_16,b_16) each assigned the sign extended a,b version by inseting zeros(for positive values) or ones(for negative values) then add up a_16 and b_16 to c.

another way is to do addition as 8 bits with carry then sign extend the result onto c

another way is to instantiate an altera adder and enter the various widths.

note for adding two 8 bit values you only need 9 bits result and not 16 bits.