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Altera_Forum
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17 years ago

std_logic_vector

Just want to ask a very simple question but it troubled me alot, let say i have to input a and b with the format of std_logic_vector(7 downto 0) and output c with the format of std_logic_vector...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Try this method(one of many) if your values are meant to be signed, otherwise use unsigned

c <= std_logic_vector(resize(signed(a),16) + resize(signed(b),16));