state machine is unstable

Hi,

while I'm designing with VDHL rather than Verilog I may have overseen coding issues but... I had similar behaviour ("strange" operation of state machine) with VHDL sometimes. I always fixed this with synchronising all "external", i.e. asynchronous signals first prior using these to initiate state machine decisions. I assume signals like "Overcurrent" or "ChopFB" are connected by I/O Pins and may therefore change asynchronous to the SysClock used as state machine clock. That may cause timing issues if the "next state calculation" and the switching SysClock may violate register's setup or hold times...

Perhaps you give it a try and synchronize the external signal to SysClock first using these "internal" signals as input to the state machine...

Just my two cents,

Carlhermann

Hi Carlhermann,

It's fine. Thank you very much.:)

Qian.Miao

Effects like the observed one usually refer to timing violation caused by state machine input signals that are asynchronous to the FSM clock. As long as the test bench is not systematically varying the input signal timing, they will be hardly detected in simulation.

In some cases, the issue can be brought up by clock glitches and other unexpected clock timing variations.

Hi Fvm,

As you said, the input causes uncertain state. And I synchronized the input, and it works well.

Thanks!

Qian.Miao