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Altera_Forum
Honored Contributor
14 years agostate machine is unstable
Dear sir/madam, I designed my project with EPM1270 in verilog language. The state machine on the project is unstable as attachment shown. On line 91, when ChopFB[0] is changed from 0 to 1, th...
Altera_Forum
Honored Contributor
14 years agoHi Fvm,
As you said, the input causes uncertain state. And I synchronized the input, and it works well. Thanks! Qian.Miao