Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorstate machine is unstable
Dear sir/madam, I designed my project with EPM1270 in verilog language. The state machine on the project is unstable as attachment shown. On line 91, when ChopFB[0] is changed from 0 to 1, th...
Altera_ForumHonored Contributor
Honored ContributorEffects like the observed one usually refer to timing violation caused by state machine input signals that are asynchronous to the FSM clock. As long as the test bench is not systematically varying the input signal timing, they will be hardly detected in simulation.
In some cases, the issue can be brought up by clock glitches and other unexpected clock timing variations.
