SSN and reserve pins as ground

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I would hope they are somewhat related, given that the switching time of an I/O is intimately related to the impedance it is driving :)

If the SSN inside a package is calculated based on di/dt and dv/dt, then without having some form of I/O impedance constraint, do the values Quartus provides give meaningful results?

I haven't used this particular feature of Quartus. If you have some insight into how useful it is, I'd be happy to hear it, and then use the tool on my next board design.

There's so many features to the tools now, its hard to keep up!

Cheers,

Dave

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For the record, you can enter your trace model for all your I/Os and it makes the SSN analyzer more accurate. That's why Altera recommands doing a pre-layout analysis with a 80 or 90% pass-fail criterion and then perform a post-layout analysis with your traces models and your actual PCB stackup with a pass-fail criterion of 50%.

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For the record, you can enter your trace model for all your I/Os and it makes the SSN analyzer more accurate. That's why Altera recommands doing a pre-layout analysis with a 80 or 90% pass-fail criterion and then perform a post-layout analysis with your traces models and your actual PCB stackup with a pass-fail criterion of 50%.

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The SSN analyzer sounds pretty useful then. I'll have to check it out.

Out of interest, how much of your FPGA is the PCI core taking (once you include the backend Avalon-MM interface FIFOs, or whatever you are implementing). When I looked at PCI interfaces a while back, it was cheaper to use a PCI-to-local bus bridge from PLX Technologies. Depending on what FPGA you are using, perhaps a Cyclone GX with x1 PCIe and a PCIe-to-PCI bridge would be cost-effective, and less hassle to design (depending on your PCB real-estate).

eg., PEX8111 x1 PCIe to PCI $23 at Mouser

http://www.mouser.com/productdetail/plx-technology/pex8111-bc66fbcf/?qs=sgaepimzzmtifczob2abwx8plyc9mlqr

Cyclone IV EP4CGX15 $25 at Altera

http://www.buyaltera.com/scripts/partsearch.dll?detail&name=544-1475-nd

Cheers,

Dave

Yeah, I'll have to think about it. In all of our previous designs, we connected the PCI bus directly to an FPGA but this is the first time we ran an SSN analysis.

The previous design was done with a Virtex-5. We want to port it to an Arria II FPGA

, I know that we ran into some problems with the PCI (in the Virtex-5 FPGA) when connected to some specific backplane PCB, it is possible that this was an SSN problem.

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I know that we ran into some problems with the PCI (in the Virtex-5 FPGA) when connected to some specific backplane PCB, it is possible that this was an SSN problem.

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What type of backplane? CompactPCI or regular PCI?

Cheers,

Dave