Honored ContributorHi y'all,
Here's the problem - I am building a counting device and I'm running out of storage room on the DE2. I am currently using registers and would like to use the SRAM chip. 1. does anybody have an implementation of the SRAM interface and experience using it? 2. what are the speed limitations of the SRAM - how many writes per second? any help would be greatly appreciated... Thanks, Tom
Honored Contributorhi, do you have de2-70 or only de2? on de2 is sram and on de2-70 is synchronous sram. If you wanna use these memories, you muss add to sopc components called ip university program. And thats everything and you can start with sram. Sram has 16b width and synchronous sram has 32 bit width. So ssram will be faster, but i dont know what you have for de.
Bye VaclavHonored Contributori think sram is up to 100mhz and synchronous sram is up to 200mhz
Honored ContributorI got de2 (not 70)
And i dont want to use nios, its too slow...Honored Contributorok, but the interface of sram is very simply, you muss read low byte and then high byte, i think on cd from de is datasheet.
Honored ContributorI dont understand.
I am not using nios! i want to read and write from sram using verilog code only. does anyone have an example of how it is done, (and how many clocks does it take to write a 20 bit number to sram?)Honored Contributori dont say something about the nios, you muss write interface to the memory in the verilog, this sram is asynchronous, so sram dont need clock, so your question is irrelevant, important value is tAA, which is Address Access Time, this sram has only 16bit data port, so you need read low word and high word, its 2xtAA, but it depends also on your code in the verilog (additional delays in your system)
i think its clearHonored Contributorhere is pdf with the description
Honored ContributorDumb question:
You wrote that you're using registers. Does that mean you haven't used the M4K blocks yet?Honored ContributorNo I haven't - since they are not big enough.
I need the size of the sram...
