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Community ManagerSPI Master -3 SPI slave_FA
Community ManagerNot a bug — this is expected behavior. The xx_external_SS_n port is a multi-bit bus, not three separate ports. When you configure the SPI IP for 3 slaves, that single ss_n port becomes a 3-bit wide signal [2:0], with one bit dedicated per slave.
Here's the reasoning from the IP documentation:
When the SPI core is configured to interface with multiple agents, the core has one ss_n signal for each agent. "Embedded Peripherals IP User Guide" These are all bundled into the single ss_n bus port you see in the instantiation file.
The parameter you set specifies the number of agents the SPI host connects to. Embedded Peripherals IP User Guide So setting it to 3 means the ss_n bus will be 3 bits wide — ss_n[0], ss_n[1], and ss_n[2] — each driving one slave's chip-select line.
The slaveselect register is a bit mask for the ss_n signals driven by an SPI host. "Embedded Peripherals IP User Guide" During a transfer, the host asserts ss_n to each agent specified in the slaveselect register. Embedded Peripherals IP User Guide
So in your top-level or testbench, simply connect individual bits of that bus to your three slave devices:
xx_external_SS_n[0]→ Slave 0xx_external_SS_n[1]→ Slave 1xx_external_SS_n[2]→ Slave 2
slaveselect register before initiating a transfer to select the target slave. There is one bit in slaveselect for each ss_n output, and a master peripheral can set multiple bits simultaneously to select multiple slave devices during a transaction. SSO Setting SSO to 1 forces the SPI core to drive its