Speed optimization

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Hello every body;

I asked if there is a synthesis directive to place the critical-path related logics of my design in a fast portions of the FPGA.

Thanks.

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Input the timing constraints (i.e. clock period, input pin setup delay and clock to output delay) into the tool. The fitter run will do it's job.

Kevin

Thanks Mr.K_J for attention.

But I have assigned the clock period constrain. what is the goal of assigning the clock-to-output and the input pin setup delay.

Thanks,