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Altera_Forum's avatar
Altera_Forum
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9 years ago

Speed optimization

Hello every body; I asked if there is a synthesis directive to place the critical-path related logics of my design in a fast portions of the FPGA. Thanks.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thanks Mr.K_J for attention.

But I have assigned the clock period constrain. what is the goal of assigning the clock-to-output and the input pin setup delay.

Thanks,