Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Source Synchronous Input Delay Virtual Clock Explanation.

I am trying to constrain a source synchronous design where the clock is provided to the device. Data flows to and from the device bidirectionally.

We are interested in both microSD and a SDRAM module.

Why it is when the FPGA is providing the clock to the outside device in source synchronous timing is input_delay

referenced to a virtual clock? You might think it should reference the generated clock similar to the set_output_delay constraint.

set_output_delay is recommended to reference a generated clock.

Can someone explain this, and possibly reference a resource?

Thanks!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    According to Synopsis (as stated somewhere in Xilinx vivado timing tool docs), You can use any clock as reference for io delay statements including unrelated internal fpga clocks!

    The tool wants any known clock as reference. Naturally, you will use a clock that makes sense and you know the relationship of data to it and so can set correct figures for input/output delay.

    So whether it is physical input clock or generated clock or virtual clock as long as your figures are correct relative to chosen clock it should be ok and you will then need to check report that the tool's view agrees with your view.