Source Synchronous Input Delay Virtual Clock Explanation.

According to Synopsis (as stated somewhere in Xilinx vivado timing tool docs), You can use any clock as reference for io delay statements including unrelated internal fpga clocks!

The tool wants any known clock as reference. Naturally, you will use a clock that makes sense and you know the relationship of data to it and so can set correct figures for input/output delay.

So whether it is physical input clock or generated clock or virtual clock as long as your figures are correct relative to chosen clock it should be ok and you will then need to check report that the tool's view agrees with your view.