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Lambert's avatar
Lambert
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Source synchronous constrains

Hi all,

Current source synchronous design, like lvds output, if clk_o and data_o are output through lvds ip Core, and the phase between load_clk & serial clock of clk_o and load_clk & serial_clk of data_o can be adjusted by the reconfigurable exteral Pll method, is there necessary to do the source synchronous constrains for the io interface? I think it's not necessary and the result will be okay. If need, will the source synchronous constrains be related to the frequency of clk_o?

Best regards,

Lambert

3 Replies

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    We do not receive any response from you to the previous answer that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.


    • Lambert's avatar
      Lambert
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi KeenyT_Intel,

      The link you provided is one system synchronous part, I want to reserch source synchronous topic, and I don't fine one principle that can be used for source synchronous, if the output frequency can change freedomly.

      B.R.

      Lambert