Forum Discussion
Lambert
Occasional Contributor
Occasional ContributorSource synchronous constrains
Hi all,
Current source synchronous design, like lvds output, if clk_o and data_o are output through lvds ip Core, and the phase between load_clk & serial clock of clk_o and load_clk & seria...
KennyT_altera
Super Contributor
Super ContributorYes, it is still needed. You may take a look at https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf page 9.
Unless you want to make your signal asynchronous, otherwise the constrain of IO wrt to clk is needed.
