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Lambert's avatar
Lambert
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Source synchronous constrains

Hi all, Current source synchronous design, like lvds output, if clk_o and data_o are output through lvds ip Core, and the phase between load_clk & serial clock of clk_o and load_clk & seria...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

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  • Lambert's avatar
    Lambert
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi KeenyT_Intel,

    The link you provided is one system synchronous part, I want to reserch source synchronous topic, and I don't fine one principle that can be used for source synchronous, if the output frequency can change freedomly.

    B.R.

    Lambert