sorter in vhdl

Have you written any code yet?

What are the interface specs?

what are the design specs?

Have you even tried google?

all codes i found gave the greater or smallest value from an array

i have an array 0 to 255 for integer input

and i want to order them

any idea plz

--- Quote Start ---

all codes i found gave the greater or smallest value from an array

i have an array 0 to 255 for integer input

and i want to order them

any idea plz

--- Quote End ---

one method of sorting is as follows:

use ram of 256 depth.

use your data as address and rd/wr from that location after one increment. So for example if data is 7, read data7(0) add 1 and write back(1)

continue in this manner then read back your ram contents which could be something like this:

0 : 2

1: 0

2: 5

3: 1

...etc

hi kaz

i want first to thank you very much i have finished the part of authentication mode i would not finish it without you help .

now if i have two input first for codes std_logic_vector ( 0 to 7)

and the second for its time which is in integer type ,such as

00000001 ------> 125 ms

00010010 ------> 100 ms

01000100 ------> 200 ms

01111000 ------> 147 ms

and i want to sort them as the following

00010010 ------> 100 ms

00000001 ------> 125 ms

01111000 ------> 147 ms

01000100 ------> 200 ms

so, i want to sort the second input in ascending order and the corresponding firt input data to it

i hope to understand me and help me to start that code.

sorry for bad english

--- Quote Start ---

hi kaz

i want first to thank you very much i have finished the part of authentication mode i would not finish it without you help .

now if i have two input first for codes std_logic_vector ( 0 to 7)

and the second for its time which is in integer type ,such as

00000001 ------> 125 ms

00010010 ------> 100 ms

01000100 ------> 200 ms

01111000 ------> 147 ms

and i want to sort them as the following

00010010 ------> 100 ms

00000001 ------> 125 ms

01111000 ------> 147 ms

01000100 ------> 200 ms

so, i want to sort the second input in ascending order and the corresponding firt input data to it

i hope to understand me and help me to start that code.

sorry for bad english

--- Quote End ---

use same principle as above(using counters per ram location) but with some modification:

have a ram 256 depth, 10 bits wide.

use ms value as address

for each address read data, increment it by 1, write the corresponding code into 8 msbs of ram data and increment value into two lsbs of ram data.

at the end you will have your ram ready sorted in ascending order of address. The value of ms is the address, the 8 bits content is your corresponding code. the two lsbs are counter for how many times same value occured. if necessary use > 2 bits for counting.

i try to write this code

is it as you suggest kaz

library ieee;

use ieee.std_logic_1164.all;

use IEEE.numeric_std.all;

entity bubblesort is

port(

clk : in std_logic;

we : in std_logic;

trigraph : in std_logic_vector(7 downto 0);

duration : in integer range 0 to 1023 ;

rd_duration : in integer range 0 to 1023;

rd_trigraph : out std_logic_vector(7 downto 0)

);

end entity;

architecture rtl of bubblesort is

type mem is array(0 to 1023) of std_logic_vector(7 downto 0);

signal ram : mem := ((others=> (others=>'0')));

signal n,i : integer range 0 to ram'length;

begin

process(clk)

begin

if(rising_edge(clk)) then

if(we = '1') then

n <= 0;

i <= 0;

ram(duration) <= trigraph;

end if;

end if;

if(rising_edge(clk)) then

if (we= '0') then

rd_trigraph <= ram(rd_duration);

end if;

end if;

if (n < ram'length) then

if (i < ram'length-1) then

if (ram(i) > ram(i+1)) then

ram(i) <= ram(i+1);

end if;

i <= i+1;

else

i <= 0;

n <= n+1;

end if;

end if;

end process;

end rtl ;

here is my attempt as guide only:

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bubblesort is
port(
    clk      : in std_logic;
    we       : in std_logic := '1';
    trigraph : in std_logic_vector(7 downto 0) := x"0F";
    duration : in integer range 0 to 1023 := 5;
    dout     : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of bubblesort is
  
signal ram_din, ram_dout : std_logic_vector(8 downto 0) := (others => '0');
type mem is array(0 to 1023) of std_logic_vector(8 downto 0);
signal ram : mem := ((others=> (others=>'0')));
begin
--infer ram
process(clk)
begin
if(rising_edge(clk)) then
   ram_dout <= ram(duration);
   if(we = '1') then
      ram(duration) <= ram_din;
   end if;
end if;
end process;
ram_din <= trigraph & we; 
dout <= ram_dout(8 downto 1);
  
end rtl ; 

notice I use we as flag that a write occurred in case data is zeros all.

after all ram write is done you need to control address (instead of duration) so that you read from address 1023 to 0 to get the code out provided bit(0) of ram_dout is '1'.

I am assuming each code will have its unique duration

first i want to thank you,i appreciate your time

I am assuming each code will have its unique duration

you are right each code has its unique duration

but i want know from you why ram_din gave me that output & dout??

sorry for that question!!

That looks ok to me.

your address(duration) is: 16,8,32,9,48

your data(trigraph) is: 10,20,30,40,50

due to one bit shift + 1 your data becomes 2*10+1 = 21 and so on then reverse that at output 101/2 -1 = 50

to avoid confusion you can use bit(8) as flag