sorter in vhdl

or that modification is right

library ieee;
    use ieee.std_logic_1164.all;
    use IEEE.numeric_std.all;
    entity bubblesort is
    port(
        clk      : in std_logic;
        we       : in std_logic := '1';
        trigraph : in std_logic_vector(7 downto 0) := x"0F";
        duration : in integer range 0 to 1023 := 5;
        read     : in std_logic := '0';
        dout    : out std_logic_vector(7 downto 0)
    );
    end entity;
    architecture rtl of bubblesort is
      
    signal address, rd_addr : integer range 0 to 1023 := 0;
    signal trigraph_d : std_logic_vector(7 downto 0);
    signal we_d : std_logic := '0';
	 signal dout_buf : std_logic_vector(7 downto 0) := x"ff";
	 
    type mem is array(0 to 1023) of std_logic_vector(7 downto 0);
    signal ram : mem := ((others=> (others=>'0')));
    begin
    --infer ram
    process(clk)
    begin
    if(rising_edge(clk)) then
       dout <= ram(address);
       if(we_d = '1') then
		  
          ram(address) <= trigraph_d;
       end if;
    end if;
    end process;
    process(clk)
    begin
    if rising_edge(clk) then
      
      we_d <= we;
      trigraph_d <= trigraph;
      
      if read = '1' then
        if rd_addr < 1023 then
          rd_addr <= rd_addr + 1;
        end if;
      end if;
      
      if read = '0' then
		 
        address <= duration;
      else
        address <= rd_addr;
      end if;
      
    end if;
    end process;
	 
	 --discard zeros values
	  process(clk)
    begin
    if(rising_edge(clk)) then
       if ram(address)/=x"00" then
          dout_buf <= ram(address);
       end if;
       
    end if;
    end process;
    dout <= dout_buf;
    end rtl;