sof and pof behaves differently for Max 10

It's not really possible to answer without knowing what the design is supposed to do and what happens differently between the two files. Also, where is the .pof being stored? I presume in the CFM. Can you provide more details?

#iwork4intel

Hi,

When you download POF, do you power cycle your board? May I know what is the issue that you are observing? Do you performed system reset after you power on your board?

Thank you sstrell and JohnT.

Yes, after downloading the POF, I did power down and power up and reset.

The design is a UART receiver and CRC checker. If CRC passed, we update certain registers to the value received. if CRC failed, then we don't update the registers.

we have 3 version of the RTL,

1. for first version, SOF and POF works great.
2. for 2nd version, we changed some other logic not related the UART function. and for this compile, SOF works, and POF not working.
3. based on 2nd version. I added signal tap analyzer in the design trying to debug where the problem is. I did not change any of the RTL. for this version, SOF and POF both works well.

So, this looks very strange to me, meaning, the 2nd version, the netlist is slightly different than the 1st or 3rd version, and this causes the POF not working.

Thanks

By the way, I am using Quartus 15.0 64-bit windows.

Now I change the config device settings from "instant on" to "slow POR delay", and it fix the issue.

Not sure if this really fix the issue, or there is netlist change due to this different setting which avoid the cornor case having the issue.

Hi,

May I know when you mention POF is not working then what is the issue observed? Is it the functionality is not working correctly?

When you change the config setting, I do not think that there is changes in the netlist and it is only changing so that the Max 10 device will have a slower time to enter usermode.

Hi,John,

It is functionally not working correctly.

Now I have the following experiments that reveals the issue(FPGA start to config from CFM to Logic cells before Logic cells power up stably).

1. after power up, I draw NCONFIG pin to low to force a re-configuration, and this fix the issue.
2. I connect a 10UF capacitor between GND and NCONFIG pin, and this also fix the issue.
3. As mentioned before, I change config settings from" instant ON" to "slow POR delay", and it fix the issue.

So, based on the 3 experiments above, my conclusion is that, right after Power up, FPGA start to config from CFM to Logic cells before Logic cells powered up stably.

Is there any other suggestions beyond my solution above?

Thanks

Hi,

May I know if you have tried to performed system reset on your design to see if the functionality recover? I would like to understand if the configuration is causing the issue or the design is not reset correctly after power on due to external component driving the FPGA.

The reason is that I do not think that the FPGA is configured incorrectly which usually will cause configuration failure rather then entering usermode if the power is still not stable.

Hi, John,

I tried reset it, and it doesn't fix the issue.

during reset, I can see the the reset is effective since the IO communication stopped during reset.

Hi,

May I know what type of functionality failure do you observed? Just would like to understand what is actually happening when resetting the system design is not helping. This is so that we are able to fixed the issue.