sof and pof behaves differently for Max 10

Hi,John,

It is functionally not working correctly.

Now I have the following experiments that reveals the issue(FPGA start to config from CFM to Logic cells before Logic cells power up stably).

1. after power up, I draw NCONFIG pin to low to force a re-configuration, and this fix the issue.
2. I connect a 10UF capacitor between GND and NCONFIG pin, and this also fix the issue.
3. As mentioned before, I change config settings from" instant ON" to "slow POR delay", and it fix the issue.

So, based on the 3 experiments above, my conclusion is that, right after Power up, FPGA start to config from CFM to Logic cells before Logic cells powered up stably.

Is there any other suggestions beyond my solution above?

Thanks