Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

sld_hub modul crashes system

Hi there!

I've got a strange problem with the auto generated sld_hub. My design contains a Qsys system with some DSP-moduls and it works fine. There is no Signal Tap Analyzer in the design, only a JTAG-UART. Sometimes, I get the following synthesis message:

Warning (13024): Output pins are stuck at VCC or GND

Warning (13410): Pin "sld_hub:auto_hub|receive[0][0]" is stuck at GND

Info (286031): Timing-Driven Synthesis is running on partition "sld_hub:auto_hub"

Everytime this message shows up, the system will not work correctly. I found that this modul is related to STP or NIOS JTAG UART, but why doesn't it shows up every time?

To reproduce this behavior, I built the system with optimiziation technique to balanced, then it shows up. If I change to speed, it does not and the system works fine. It also differ, if I don't change anything, just rebuild.

Can anybody explain this and how I can suppress this module?

Thanks a lot!

bolbotos

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I don't have a good answer to your question, but I have several projects that only appear on some compiles and not others, with several IPs from Altera (sc fifos and plls mostly). As they aren't easy to reproduce I didn't manage to get support from Altera on those. I found out that deleting the db and incremental_db folders before each compile solves the problems, so it looks like a bug in the part of Quartus that tries to re-use a result of the previous compile (and no, disabling smart compile doesn't solve it). Try this on your project and see if the problem still appears.