Forum Discussion
Altera_Forum
Honored Contributor
13 years agosld_hub modul crashes system
Hi there! I've got a strange problem with the auto generated sld_hub. My design contains a Qsys system with some DSP-moduls and it works fine. There is no Signal Tap Analyzer in the design, onl...
Altera_Forum
Honored Contributor
13 years agoI don't have a good answer to your question, but I have several projects that only appear on some compiles and not others, with several IPs from Altera (sc fifos and plls mostly). As they aren't easy to reproduce I didn't manage to get support from Altera on those. I found out that deleting the db and incremental_db folders before each compile solves the problems, so it looks like a bug in the part of Quartus that tries to re-use a result of the previous compile (and no, disabling smart compile doesn't solve it). Try this on your project and see if the problem still appears.