Single Pulse in output with pulse width ibility control

Hi everyone. I have used many ways to create single out pulse with pulse width bility. So far as I know I have to use counter to count clock pulses and make the output one and zero.

I have used state machine to write my code but always there is an unwanted pulse before my code configuration.

All suggestions are Welcomed.

the output waveform is attached.

my code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity ltd_auto is

port

(

clk : in std_logic;

data_out: out std_logic

 );

end ltd_auto;

Architecture behavioral of ltd_auto is

signal c : integer:= 0;

constant a : integer:= 2;

constant b : integer:= 3;

type state_type is (idle, delay, zero);

signal next_s: state_type;

begin

process (clk)

begin

if (rising_edge(clk))then

case next_s is

when idle =>

c <= c + 1;

next_s <= delay;

when delay =>

if (c = a) then

data_out <= '1';

end if;

if (c = b) then

data_out <= '0';

next_s <= zero;

else

c <= c + 1;

end if;

when zero =>

c <= 0;

end case;

end if;

end process;

end behavioral;