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Altera_Forum
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12 years ago

Single Pulse in output with pulse width ibility control

Hi everyone. I have used many ways to create single out pulse with pulse width bility. So far as I know I have to use counter to count clock pulses and make the output one and zero. I have used st...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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or just create a initial delay either by sensing a button being pressed or when a counter reaches a certain value after FPGA is configured .

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Hi dude, Can you be more described? I have tried to use reset before rising_edge (clk) and make my output '0' but it did not work also. And because of planned usage of fpga using buttons are not easy. I want to use it in a compact place beside other devices and it could be difficult for me to use buttons. still any idea with/without buttons are welcomed.

Regards