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Altera_Forum
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12 years ago

Single Pulse in output with pulse width ibility control

Hi everyone. I have used many ways to create single out pulse with pulse width bility. So far as I know I have to use counter to count clock pulses and make the output one and zero. I have used st...
Altera_Forum's avatar
Altera_Forum
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12 years ago

The initial high is while the FPGA is being configured. Once configured the output is driven low and fires a single pulse as your state machine describes.

If you want your output to be low during configuration you have to add a pull-down resistor to the FPGA's pin.