Single Port RAM issue on cyclone IV

apparently you are asking about in system memory editor rather than writing to ram through logic.

Have you set megawizard activating this feature in your ram?

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I am not asking about using memory editor, i have used memory editor to verify that it is not getting written, and yes i have set the feature in megawizard to allow me in system editing

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It is not working in simulation either except for intial states of 0 and 1. Your design ends up in state 2 doing nothing.

also be aware that your mem clock is gated (can do but not safe).

it works in the simulations right... the first time i read memory address 1 is shows output - 2 (@ 0.0005us) and after writing and reading again (second read is at beginning of state 2) it shows 15 (@0.0021us)

PS. maybe the resolution of the uploaded pics is not that good, but i uploaded decent images, i how dont know why it got compressed that way, or how can i upload w/o reducing quality

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it works in the simulations right... the first time i read memory address 1 is shows output - 2 (@ 0.0005us) and after writing and reading again (second read is at beginning of state 2) it shows 15 (@0.0021us)

PS. maybe the resolution of the uploaded pics is not that good, but i uploaded decent images, i how dont know why it got compressed that way, or how can i upload w/o reducing quality

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Any chance you can upload higher resolution pictures? It's near impossible to read... What exactly are you trying to do? It looks like you're trying to measure when data becomes available after you write it? If that's the case.. WHY?

As long as you adhere to a synchronous system you shouldn't have any problems? The inputs are registered but IIRC you can opt to not register the output. As long as your clock period is long enough, you should be fine. The simulator should provide you with enough timing information to show that the constraints are met.

More info please :-)

-Mux

it works in the simulations right... the first time i read memory address 1 is shows output - 2 (@ 0.0005us) and after writing and reading again (second read is at beginning of state 2) it shows 15 (@0.0021us)

PS. maybe the resolution of the uploaded pics is not that good, but i uploaded decent images, i how dont know why it got compressed that way, or how can i upload w/o reducing quality

Explaining my issue again, i am trying to perform read and write operations on single port ram. I am getting the read fine, but i am unable to write any data on the RAM. I tried the RTL simulation on the modelsim, and that worked fine, so i cannot understand what the issue was

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it works in the simulations right... the first time i read memory address 1 is shows output - 2 (@ 0.0005us) and after writing and reading again (second read is at beginning of state 2) it shows 15 (@0.0021us)

PS. maybe the resolution of the uploaded pics is not that good, but i uploaded decent images, i how dont know why it got compressed that way, or how can i upload w/o reducing quality

Explaining my issue again, i am trying to perform read and write operations on single port ram. I am getting the read fine, but i am unable to write any data on the RAM. I tried the RTL simulation on the modelsim, and that worked fine, so i cannot understand what the issue was

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I posted in my last reply that you are running state signal as 0,1,2 then it stays 2 for ever.

you are writing to ram in state 0 or 1 but nothing done in 2.

As such you need to check that your compiler hasn't optimised your ram off during synthesis.

no my ram is not synthesised off, and in my code nothing is done in state 2.. so that i could give it many clock pulses incase any change does happen after a few cycles, in the simulation, the output of ram does change (as it should be) but that does not happen on programming by board with it.

i used gated pulse so that i could easily change clock period, i tried going upto 1s clock pulse but still write does not take place

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no my ram is not synthesised off, and in my code nothing is done in state 2.. so that i could give it many clock pulses in case any change does happen after a few cycles

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you have only one single pulse of wren and right at very start of time. You might equally have problems that do happen. for example your neg clock edge may miss the wren. Try make it longer for two clocks.