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Altera_Forum
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11 years ago

Single Port RAM issue on cyclone IV

I have been using single port ram using megafunction, my initialization file has 4 words of 4 bits each - 4'h1,4'h2,4'h3,4'h4 The reading part is fine, but I am unable to write any data, the RTL ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

no my ram is not synthesised off, and in my code nothing is done in state 2.. so that i could give it many clock pulses incase any change does happen after a few cycles, in the simulation, the output of ram does change (as it should be) but that does not happen on programming by board with it.

i used gated pulse so that i could easily change clock period, i tried going upto 1s clock pulse but still write does not take place