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Altera_Forum
Honored Contributor
12 years agoSingle Port RAM issue on cyclone IV
I have been using single port ram using megafunction, my initialization file has 4 words of 4 bits each - 4'h1,4'h2,4'h3,4'h4 The reading part is fine, but I am unable to write any data, the RTL ...
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- no my ram is not synthesised off, and in my code nothing is done in state 2.. so that i could give it many clock pulses in case any change does happen after a few cycles --- Quote End --- you have only one single pulse of wren and right at very start of time. You might equally have problems that do happen. for example your neg clock edge may miss the wren. Try make it longer for two clocks.