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Altera_Forum's avatar
Altera_Forum
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8 years ago

Simultaneous Read and Write to DDR3 SDRAM

simultaneous read and write on ddr3 sdram using soft sdram controller with uiphy ip via qsys interconnect.

An AXI-MM master is connected to Qsys Interconnect to perform read and write operation on SDRAM slave,

Cyclone V is the FPGA device, with PL only system.

Read is initiated first, with read length- 512, Write is initiated later say after 20 cycles of delay from Read operation. with a length 512.

Read address locations does not overlap with that of write.

This specific operation fails as Interconnect drops the wr_ready signal halting the operation.

While The same worked well using Xilinx Interconnect on a Xilinx Device. (independent read and write on Cyclone 5 was successful but the operation demands a simultaneous R/W)

Is there any Interconnect requirements or bridges that I would permit simultaneous read and write?.

Thanks for help

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Ahm ... having worked with a DDR3 SDRAM protocol before, the underlying protocol doesn't allow simultaneous reads and writes. As a result, any attempts you make will need to be buffered in order to give the appearance of being simultaneous. Perhaps you should check your FIFO/buffering settings therefore.

    Dan
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    Ahm ... having worked with a DDR3 SDRAM protocol before, the underlying protocol doesn't allow simultaneous reads and writes. As a result, any attempts you make will need to be buffered in order to give the appearance of being simultaneous. Perhaps you should check your FIFO/buffering settings therefore.

    Dan

    --- Quote End ---

    FIFO setting as in which IP ?, My master has no Provision for it, I did not see any on the Slave controller either. Please specify.

    Thank you
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    FIFO settings as in which IP, My master does not support it. I did not find any buffer on the slave controller either, Would you please specify where ?

    Thank you
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    I guess that would depend upon which IP's you are using. A master connected directly to an SDRAM device cannot both read and write. The wires just don't work in both directions, they are shared and (worse) take a couple of (memory) clocks to switch directions. If the controller you are using doesn't have a FIFO within it, then you'll need to either find another controller or place a FIFO within your own design.

    I imagine, from your statement above, that Xilinx's controller must've had some extra stuff within it. I know from my own testing that their controller nearly doubled the memory access latency from the minimum, but that's neither here nor there as I have yet to measure memory latency with Altera.

    Dan