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Honored Contributor
Honored ContributorSimultaneous Read and Write to DDR3 SDRAM
simultaneous read and write on ddr3 sdram using soft sdram controller with uiphy ip via qsys interconnect. An AXI-MM master is connected to Qsys Interconnect to perform read and write operation...
Altera_ForumHonored Contributor
Honored ContributorI guess that would depend upon which IP's you are using. A master connected directly to an SDRAM device cannot both read and write. The wires just don't work in both directions, they are shared and (worse) take a couple of (memory) clocks to switch directions. If the controller you are using doesn't have a FIFO within it, then you'll need to either find another controller or place a FIFO within your own design.
I imagine, from your statement above, that Xilinx's controller must've had some extra stuff within it. I know from my own testing that their controller nearly doubled the memory access latency from the minimum, but that's neither here nor there as I have yet to measure memory latency with Altera. Dan
