Honored ContributorHi all,
I was used to simulate my project with the simulation tool in earlier version of quartus but now, this tool is no longer available with the version 10.0 and I have to use ModelSim. My questions are : Is there an easy way like "vector waveform file" to initiate the simulation or do I have to do all the stuff with command lines? Do you know a good tutorial to learn how to use ModelSim? Thank you
Honored ContributorThe easiest way to do this is in a testbench. You can write the testbench in your favourite HDL language and create waveforms to your heart's content, using direct assignments, waveform functions or reading from files. The Testbench is not going to be synthesised, so you can do loads of stuff you normally cant do.
What language do you normally create designs in?Honored ContributorWrite a tesbench.
You've to set the Settings.. | simulation in order to compile the testbench. An example, combinatorial, testbench is the for a priority encoder following (remove line numbers): 1 `timescale 1ns/1ps // define simulation time units 2 module prenc83_tb(); // module with no inputs or outputs 3 reg [7:0] Atb; // reg net type. To be assigned in the initial block 4 wire [2:0] Ytb; 5 wire idle; 6 prenc83 d1(.A(Atb),.Y(Ytb)); // UUT named d1 7 initial // Just once at the beginning of the simulation 8 begin 9 Atb = 8'h01; // Eight bits hexadecimal value 10 # 100; // 100 time units delay -> 100 ns 11 Atb = 8'h02;# 100; 12 Atb = 8'h04;# 100; 13 Atb = 8'h08;# 100; 14 Atb = 8'h10;# 100; 15 Atb = 8'h20;# 100; 16 Atb = 8'h40;# 100; 17 Atb = 8'h80;# 100; 18 Atb = 8'h44;# 100; 19 Atb = 8'hF0;# 100; 20 Atb = 8'h00;# 100; 21 Atb = 8'hCF;# 100; 22 $stop; // System call that stops the simulation 23 end 24 endmodule For a sequential project you need a clock. It can be defined, in the testbench, as: // Generates the clock waveform parameter PERIOD=20; always begin CLKtb=0;# (PERIOD/2.0); // Delays by PERIOD/2 time units CLKtb=1;# (PERIOD/2.0); endHonored Contributordoes Modelsim support Quartus's design entry files (bdf, bsf) or do I need to convert everything to VHDL\Verilog?
Honored ContributorYou need to convert them.
The Quartus simulator never really supported them either - it only simulated a post place and route netlist.Honored ContributorHonored Contributorif you still have 9.1sp2 or earlier installed you can create an HDL test bench from your .vwf
as mentioned you can also create an HDL file for the .bdf. your Megafunctions should all have a source file in an HDL. be sure to create them all in the same HDL, as both versions of ModelSim-Altera only support a single HDL. when you create an HDL file from a .bdf, the .bsf are bypassed and the the source HDL for the .bsf is instantiated directly i would also take a look at Altera's NativeLink feature that automates running ModelSim for youHonored ContributorHi all and thanks for your answers,
I've created a testbench file from a vwf file. Then I've added it to my project with quartus 10.0. Now when I click on "Run EDA Simulation tool -> EDA RTL Simulation", ModelSim is launched but all ouputs stay in UnknownSate. Any Idea?Honored ContributorCan you post the testbench and the HDL for your design?
Probably the node names in testbench and HDL are not the same.Honored Contributorright, and also post a list of how you have your NativeLink fields filled out
Honored ContributorI found my problem !
I had converted the BDF files into VHD files, but I haven't change them in "Assignment->Settings->Files", so the compilation continued to use the BDF files. Thank you all for your help. Just one more thing, there are a lot of stuff at the beginning of the Testbench file. Is that compulsary? My testbench file is in the 3 post below, the forum doesn't allow me to post messages above 10000 caracters...
