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Altera_Forum's avatar
Altera_Forum
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14 years ago

Simulatio and Synthesis

I am learning VHDL syntax from "Circuit Design with VHDL", I was wondering why is it that most of the commands is only for simulation and not for synthesis?

What is the benefit of being able to simulate but not synthesize? Isnt the whole point of writing code is to synthesize?

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You also need to test your synthesisable designs.

    How can you generate a clock without wait commands?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    So,

    We first write code with simulation in mind and once we are done simulating we change the code so that we are able to synthesize it?

    or

    Do we write code so that we can synthesize it and then write test benches to simulate it?

    I am confused!! :(

    Could you please give an elaborated answer describing the whole process?

    Thanks a ton
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The second one.

    You write your code for your synthesisable design using the synthesisable parts of VHDL.

    You write a testbench for your design that you isntantiate the block in. From the testbench POV it provides input and gets an output. This way you can look inside the DUT to see if everything is working.

    So the DUT (design under test) and testbench are separate files (usually). You do not synthesise the testbench.