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Altera_Forum
Honored Contributor
Honored ContributorSimulatio and Synthesis
I am learning VHDL syntax from "Circuit Design with VHDL", I was wondering why is it that most of the commands is only for simulation and not for synthesis? What is the benefit of being able to...
Altera_ForumHonored Contributor
Honored ContributorThe second one.
You write your code for your synthesisable design using the synthesisable parts of VHDL. You write a testbench for your design that you isntantiate the block in. From the testbench POV it provides input and gets an output. This way you can look inside the DUT to see if everything is working. So the DUT (design under test) and testbench are separate files (usually). You do not synthesise the testbench.
