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Altera_Forum's avatar
Altera_Forum
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14 years ago

Simulatio and Synthesis

I am learning VHDL syntax from "Circuit Design with VHDL", I was wondering why is it that most of the commands is only for simulation and not for synthesis? What is the benefit of being able to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

So,

We first write code with simulation in mind and once we are done simulating we change the code so that we are able to synthesize it?

or

Do we write code so that we can synthesize it and then write test benches to simulate it?

I am confused!! :(

Could you please give an elaborated answer describing the whole process?

Thanks a ton