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Altera_Forum's avatar
Altera_Forum
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16 years ago

Signed integer and 2 complement

Hi. I am confusing with the signed integer and 2 complement in verilog.

1. if i declare b is [3:0] signed reg , what would be the bit representation if b is -3? 1011? or....

2. Previously we use the 2 complement to represent negative number and now the existance of signed number in verilog, is it indicatng that we are not going to use 2 complement? Pls clarify on it.

e.g signed A - signed B

or 2'complent A - 2'complement B

Which one is true or both?

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    -3 would be 1101 if you have MSB first 1101 LSB least

    4'b1101 in verilog expression

    signed registers were introduced with verilog 2001, so before that there were no signed registers. also with verilog 2001 the signed shift operators >>> and <<< were introduced, as << and >> were pure verilog

    so both is possible, depending on the language
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    - 3 -> 1101

    signed == two's complement in Verilog and VHDL.

    Sign + magnitude representation (-3 -> 1011) is used only in floating point arithmetic. Fixed point arithmetic uses two's complement representation. Two's complement circuits are quite cheaper than sign magnitude circuits.