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Altera_Forum
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16 years ago

Signed integer and 2 complement

Hi. I am confusing with the signed integer and 2 complement in verilog. 1. if i declare b is [3:0] signed reg , what would be the bit representation if b is -3? 1011? or.... 2. Previo...
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Altera_Forum
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16 years ago

-3 would be 1101 if you have MSB first 1101 LSB least

4'b1101 in verilog expression

signed registers were introduced with verilog 2001, so before that there were no signed registers. also with verilog 2001 the signed shift operators >>> and <<< were introduced, as << and >> were pure verilog

so both is possible, depending on the language