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Altera_Forum
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16 years ago

Signed integer and 2 complement

Hi. I am confusing with the signed integer and 2 complement in verilog. 1. if i declare b is [3:0] signed reg , what would be the bit representation if b is -3? 1011? or.... 2. Previo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

- 3 -> 1101

signed == two's complement in Verilog and VHDL.

Sign + magnitude representation (-3 -> 1011) is used only in floating point arithmetic. Fixed point arithmetic uses two's complement representation. Two's complement circuits are quite cheaper than sign magnitude circuits.