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Altera_Forum's avatar
Altera_Forum
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16 years ago

SignalTap problems

Hi,

I am trying to figure out the reason behind a problem I am having with SignalTap.

I am using the triple speed ethernet core on a Stratix GX II FPGA. My FPGA board is connected to a PC over the Ethernet. The strange thing is that I get the correct data (ok 90% correct) packet at the receiving PC. However when looking with the SignalTap inside the FPGA, I get some random rubbish data that does not correspond to what the PC has received. Worse still, the header of the packet is correct, but the payload itself is completely wrong.

Any suggestions what could be causing this problem?

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Are you perhaps using the wrong clock in signaltap to look at the outgoing data? Also, is it possible you've got the bits reversed in the signaltap setup for the data fields?

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    i agree with you,but that a question:

    how did we choice the clock when we using the signalTapII?

    what is the principle?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Jake, thanks for the reply. I've spent the last couple of days debugging this one and it turns out there are no problems with Signal Tap. We are still not sure what the problem was, but we are sure it is not in the FPGA. Most likely a software issue on the other side. However the weird thing is that the packet sniffer software was not picking up the message on the wire. Regardless, Signal Tap is ok so we can continue with the real debuging :)

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Well at what point in the data path are you looking at the transmit data? The principle is that you use the same clock that clocks the signals you are looking at to sample the signals in signaltap. So if you are looking at the data pins before they go to your ethernet PHY, you should be using the txclk that is used to clock the transmit data interface to the PHY. This is the txclk provided by the PHY for 10/100Mbps operation or the 125MHz clock inside the fpga for 1000Mbps operation.