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Altera_Forum
Honored Contributor
Honored ContributorSignalTap problems
Hi, I am trying to figure out the reason behind a problem I am having with SignalTap. I am using the triple speed ethernet core on a Stratix GX II FPGA. My FPGA board is connected to a PC...
Altera_ForumHonored Contributor
Honored ContributorWell at what point in the data path are you looking at the transmit data? The principle is that you use the same clock that clocks the signals you are looking at to sample the signals in signaltap. So if you are looking at the data pins before they go to your ethernet PHY, you should be using the txclk that is used to clock the transmit data interface to the PHY. This is the txclk provided by the PHY for 10/100Mbps operation or the 125MHz clock inside the fpga for 1000Mbps operation.
