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Altera_Forum's avatar
Altera_Forum
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16 years ago

SignalTap problems

Hi, I am trying to figure out the reason behind a problem I am having with SignalTap. I am using the triple speed ethernet core on a Stratix GX II FPGA. My FPGA board is connected to a PC...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Are you perhaps using the wrong clock in signaltap to look at the outgoing data? Also, is it possible you've got the bits reversed in the signaltap setup for the data fields?

Jake